1. Field of the Invention
The present invention relates to an internal power-source potential supply circuit for supplying an internal power-source potential to a predetermined load.
2. Description of the Background Art
FIG. 98 is a circuit diagram of a conventional internal power-source potential supply circuit for use in a semiconductor device. As shown, an external power-source potential VCE is applied as an internal power-source potential VCI to a load 11 through a PMOS transistor Q1. A comparator 1 has a negative input receiving a reference potential Vref and a positive input receiving the internal power-source potential VCI as a feedback signal, and provides a control signal S1 based on the result of comparison between the reference potential Vref and the internal power-source potential VCI to the gate of the PMOS transistor Q1.
In such an arrangement, if the internal power-source potential VCI is lower than the reference potential Vref, the control signal S1 from the comparator 1 has a lower potential to cause the PMOS transistor Q1 to conduct heavily. This increases the current supply capability from the external power-source potential VCE. Then, the circuit acts to raise the lowered internal power-source potential VCI. Conversely, if the internal power-source potential VCI is higher than the reference potential Vref, the control signal S1 from the comparator 1 has a higher potential to cause the PMOS transistor Q1 to conduct lightly. This stops the current supply capability from the external power-source potential VCE. Then, the circuit prevents further increase in raised internal power-source potential VCI. The comparator 1 may include a differential amplifier having a current mirror circuit or the like. In this manner, the internal power-source potential supply circuit may supply the internal power-source potential VCI equal to the reference potential Vref.
FIG. 99 is a circuit diagram of another conventional internal power-source potential supply circuit for use in a semiconductor device. As shown. the external power-source potential VCE is applied as the internal power-source potential VCI to the load 11 through the PMOS transistor Q1. The comparator 1 has a negative input receiving the reference potential Vref and a positive input receiving a divided internal power-source potential DVCI as a feedback signal.
The drain of the PMOS transistor Q1 is grounded through a resistor R11 and a resistor R12. The internal power-source potential VCI divided by the resistors R11 and R12 is applied as the divided internal power-source potential DVCI to the positive input of the comparator 1.
The circuit of FIG. 99 is advantageous in that the operating point of the comparator 1 may be freely selected, allowing the characteristics of the comparator 1 to be held satisfactory independently of the conditions set for the internal power-source potential VCI and external power-source potential VCE. In the arrangement of FIG. 98, a small difference between the external power-source potential VCE and the internal power-source potential VCI deteriorates the characteristics of the comparator 1, resulting in a delay in operation and a large amount of temporary reduction in internal power-source potential VCI.
The arrangement of FIG. 99 may supply the internal power-source potential VCI in a stable manner when the reference potential Vref is constant.
FIG. 100 is a graph indicating a drawback of the circuit of FIG. 99. In FIG. 100, (R11+R12)/R12=3/2. As shown in FIG. 100, a time interval T11 is defined during which the reference potential Vref rises to follow the varying external power-source potential VCE. During the time interval T11, the internal power-source potential VCI also rises to follow the varying external power-source potential VCE, but has a tendency to provide access to the external power-source potential VCE as the external power-source potential VCE increases. The internal power-source potential VCI grows higher than required, resulting in dangers of an increase in current consumption and a lower degree of reliability.
Additionally, the resistors R11 and R12 have fixed resistances, resulting in the fixed internal power-source potential VCI.
In this manner, the conventional internal power-source potential supply circuits are disadvantageous in that variations in the external power-source potential may cause decreased performance of the circuit, finding difficulties in supplying the internal power-source potential with high accuracy.
According to a first aspect of the present invention, an output potential supply circuit for supplying an output potential, comprises: a comparator circuit having a first node and a second node receiving an associated output potential associated with the output potential, the comparator circuit receiving first and second potentials provided respectively at the first and second nodes to provide the output potential on the basis of a comparison result between the first and second potentials; and a resistor element having a first end connected to the first node, and a second end connected to the second node.
Preferably, according to a second aspect of the present invention, the first node receives a reference potential through a reference potential resistor element.
Preferably, according to a third aspect of the present invention, the second node receives the associated output potential through a capacitor.
According to a fourth aspect of the present invention, an output potential supply circuit for supplying an output potential, comprises: a comparator circuit having first and second nodes and receiving first and second potentials provided respectively at the first and second nodes to output the output potential on the basis of a comparison result between the first and second potentials, the first node receiving a first reference potential through a first reference potential resistor element, the second node receiving a second reference potential different from the first reference potential through a second reference potential resistor element, the second node receiving an associated output potential associated with the output potential through a capacitor.
Preferably, according to a fifth aspect of the present invention, the output potential supply circuit further comprises: current supply means between the associated output potential received by the second node and a fixed potential for supplying a predetermined current to between the associated output potential and the fixed potential; and current control means receiving the associated output potential for controlling the amount of the predetermined current so that the associated output potential is stable on the basis of a potential difference between the associated output potential and the fixed potential.
According to a sixth aspect of the present invention, an output potential supply circuit for supplying an output potential for use in a semiconductor memory, comprises: a first resistor element having a first end receiving an internal power-source potential, and a second end specified as an output node; and a second resistor element having a first node connected to the output node, and a second end receiving a fixed potential, the output node providing a potential specified as the output potential, wherein a resistance ratio of the first resistor element to the second resistor element is variable.
Preferably, according to a seventh aspect of the present invention, the semiconductor memory includes a memory cell having a capacitance element and a bit line, the memory cell having a first electrode electrically connected to the bit line for read and write operations; a potential at the first electrode of the memory cell is specified as a storage node potential, and a potential at a second electrode of the memory cell is specified as a cell plate potential; the output node has a capacitance element; and the output potential is the cell plate potential.
Preferably, according to a eighth aspect of the present invention, the semiconductor memory includes a memory cell having a capacitance element and a bit line, the memory cell being formed on a semiconductor substrate, the memory cell having a first electrode electrically connected to the bit line for read and write operations; a potential at the first electrode of the memory cell is specified as a storage node potential, and a potential at a second electrode of the memory cell is specified as a cell plate potential; and the output potential is a precharge potential to which the bit line is set before the write operation.
In accordance with the output potential supply circuit of the first aspect of the present invention, the comparator circuit receives at the second node the associated output potential associated with the output potential and receives the first and second potentials provided respectively at the first and second nodes to output the output potential on the basis of the comparison result between the first and second potentials. The resistor element is connected between the first and second nodes. Thus, a potential difference exists between the first and second nodes during a time period over which at least the variation in the associated output potential is propagated from the second node through the resistor element to the first node.
Therefore, the comparator circuit may vary the output potential on the basis of the potential difference between the first and second nodes.
In accordance with the output potential supply circuit of the second aspect of the present invention, the first node receives the reference potential through the reference potential resistor element. Thus, the output potential may be set to the reference potential when the comparator circuit is stable.
In accordance with the output potential supply circuit of the third aspect of the present invention, the second node receives the associated output potential through the capacitor. The variation in associated output potential may be transmitted to the second node earlier by the capacitor coupling. This achieves control with a good response.
In accordance with the output potential supply circuit of the fourth aspect of the present invention, the comparator circuit receives at the second node the associated output potential associated with the output potential through the capacitor, and receives the first and second potentials provided respectively at the first and second nodes to output the output potential on the basis of the comparison result between the first and second potentials. In a stable state, the first and second reference potentials are applied to the first and second nodes through the first and second reference potential resistor elements, respectively.
Thus, a potential difference exists between the second node receiving the associated output potential and the first node during a high-frequency operation if the associated output potential varies. Then, the comparator circuit may vary the output potential on the basis of the potential difference between the first and second nodes.
Additionally, the offset potential may be provided between the first and second reference potentials to prevent the comparator circuit from operating in response to a relatively small variation in associated output potential.
The output potential supply circuit of the fifth aspect of the present invention further comprises the current supply means between the associated output potential received by the second node and the fixed potential for supplying the predetermined current to between the associated output potential and the fixed potential, and the current control means receiving the associated output potential for controlling the amount of the predetermined current so that the associated output potential is stable on the basis of the potential difference between the associated output potential and the fixed potential. The current control means may control the amount of the predetermined current to suppress the variation in associated output potential.
In accordance with the output potential supply circuit of the sixth aspect of the present invention, the resistance ratio of the first resistor element to the second resistor element is variable. Varying the resistance ratio may variably set the output potential for use in the semiconductor memory.
In accordance with the output potential supply circuit of the seventh aspect of the present invention, the cell plate potential (output potential) may be varied using the time constant of the capacitance element of the output node and the first and second resistance elements so that the cell plate potential reverses the variation in storage node potential. This improves the retention characteristic of the memory cell of the semiconductor memory receiving the output potential.
In accordance with the output potential supply circuit of the eighth aspect of the present invention, the precharge potential (output potential) may be set closer to the substrate potential of the semiconductor substrate to prolong the time period over which the storage node potential changes toward the substrate potential by the leak current to reach the insensitive region adjacent the precharge potential. As a result, the retention characteristic of the memory cell of the semiconductor memory receiving the output potential may be improved.
It is therefore an object of the present invention to provide an output potential supply circuit which is capable of variably supplying an output potential.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.